Design and Verification of Configurable Multi-channel DMA controller

Electronics and Communication Engineering

This paper proposes a method of high-speed data transmission by AMBA Direct Memory Access controller using asynchronous first in first out (FIFO).Though interrupt-driven Input/Output devices have far better efficiency than programmed I/O, Processor still requires another intervention to transfer data from memory to peripheral and vice-versa to increase throughput. But both of these techniques suffer from 1. Limited transfer rate 2. Processor’s requirement in executing instructions for each data transfer. Thus, for transferring a huge amount of data, a much more efficient method is needed. And that is Direct Memory Access. Generally it has four channels to transfer the data. So the data transfer is limited upto four devices. Hence we have come up with a configurable multi-channel DMAC so that any number of devices can be able to transfer the data by modifying the arbitration scheme. The transfer of data noticeably reduces the load on the processor. The design is implemented in Verilog Language. From the experiments it is clear that the customized DMAC design performs around 2~3 times faster than traditional DMA controller, and reduces the burden of the processor significantly.

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