ASIC Implementation Of PULP RISC-V Core

Electronics and Communication Engineering

The microprocessor used in this project is built using the RISC-V CV32E40P architecture. According to the literature review, we discovered that the previously modified 32-bit CV32E40P manufactured at non-RISC-V has a frequency of 160 MHz, so the performance is insufficient for many out-of-the-box applications. Therefore, we chose to work on the processor's performance aspect in order to better support other applications of this type. By making various modifications to the physical design of the CV32E40P, we are attempting to increase the CPU clock speed in this project from 500MHz to 600MHz. In essence, by compromising on the power and surface area components of the CPU architecture, we are essentially sacrificing performance. In this project, we won't change the CV32E40P's RTL code because we'll improve processor performance by altering physical design factors like floor planning, proper placement, etc. We'll also put more of an emphasis on resolving issues that came up when we increased the CPU clock speed, such as noise, in addition to other problems.

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