FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS
Abstract & Details
Research Area
Electronics and Communication Engineering
Keywords
Karatsuba Multiplier
Vedic multiplier
Urdhva Triyakbhyam sutra
Area efficient architecture
Array multiplier
Abstract
An area efficient multiplier design is conferred. This design is based on Karatsuba algorithm founded by Anatoly Karatsuba and ancient algorithm of Vedas, proposed within the Vedic mathematics. Multiplication is a very important mathematical operation to be performed with high speed and less power consumption in high-speed systems like Digital Signal Processing. The Karatsuba algorithm speed up the multiplication of large numbers by splitting the operands into two parts of equal length. In the Vedic multipliers the partial product generation and the also the sums are generated in few steps which reduces the carry propagation from LSB to MSB. In this proposed design the area and the delay is reduced. Finally, the results of Karatsuba Vedic multiplier is compared with Vedic multiplier.
License
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Commons
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Author Information
| # | Name | Institute / Affiliation |
|---|---|---|
| 1 | Shankar R | Prince Shri Venkateshwara Padmavathy Engineering College |
| 2 | Sundhararajan G | Prince Shri Venkateshwara Padmavathy Engineering College |
| 3 | Vignesh S | Prince Shri Venkateshwara Padmavathy Engineering College |
| 4 | Aravind AR | Prince Shri Venkateshwara Padmavathy Engineering College |
How to Cite
Use the following formats to cite this article in your research.
APA Style
R, Shankar, G, Sundhararajan, S, Vignesh, & AR, Aravind (2021). FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS. International Journal of Advance Research and Innovative Ideas In Education, 7(2), 465-469.
MLA Style
R, Shankar, et al. "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS." International Journal of Advance Research and Innovative Ideas In Education, vol. 7, no. 2, 2021, pp. 465-469.
IEEE Style
Shankar R, Sundhararajan G, Vignesh S, and Aravind AR, "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS," International Journal of Advance Research and Innovative Ideas In Education, vol. 7, no. 2, pp. 465-469, 2021.
Vancouver Style
R Shankar, G Sundhararajan, S Vignesh, AR Aravind. FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS. International Journal of Advance Research and Innovative Ideas In Education. 2021;7(2):465-469.
Harvard Style
R, Shankar, G, Sundhararajan, S, Vignesh, & AR, Aravind (2021) 'FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS', International Journal of Advance Research and Innovative Ideas In Education, 7(2), pp. 465-469.
Chicago Style
R, Shankar, et al. "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS." International Journal of Advance Research and Innovative Ideas In Education 7, no. 2 (2021): 465-469.
Turabian Style
R, Shankar, et al. "FPGA IMPLEMENTATION OF KARATSUBA VEDIC MULTIPLIERS." International Journal of Advance Research and Innovative Ideas In Education 7, no. 2 (2021): 465-469.
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