Design Analysis and Implementation of Two Stage  Operational Amplifier

RAJ KESARWANI; RAHUL PANDEY; SAHIL AGARWAL; SHAILENDRA BISARIYA; MUDIT SAXENA

Design Analysis and Implementation of Two Stage Operational Amplifier

May 2024

Vol-10, Issue-3

Paper ID: 24018

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronics and Communication Engineering

Keywords

gain Op amp Cadence 90nm Op amp CMOS

Abstract

The operational amplifier is regarded as the most crucial electronic component. This paper outlines the process for designing a two-stage CMOS operational amplifier (Op amp) and examine how different factors affect the Op amp design's properties. The primary focus of this study is the design of an optimum Op amp gain. Op amp specs are considered, including gain, phase margin, slew rate, power dissipation, and others, while keeping this as the primary consideration. The design and implementation of a two-stage CMOS operational amplifier, operating at ±1V supply voltage, are shown in this study. The simulation process is performed using an EDA program called Cadence Virtuoso, which uses 90nm technology. With a phase margin of 560 and a power dissipation of 38.02μW, the resultant gain is 84db.

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Author Information

#	Name	Institute / Affiliation
1	RAJ KESARWANI	ABES ENGINEERING COLLEGE, GHAZIABAD
2	RAHUL PANDEY	ABES ENGINEERING COLLEGE, GHAZIABAD
3	SAHIL AGARWAL	ABES ENGINEERING COLLEGE, GHAZIABAD
4	SHAILENDRA BISARIYA	ABES ENGINEERING COLLEGE, GHAZIABAD
5	MUDIT SAXENA	ABES ENGINEERING COLLEGE, GHAZIABAD

How to Cite

Use the following formats to cite this article in your research.

APA Style

KESARWANI, RAJ, PANDEY, RAHUL, AGARWAL, SAHIL, BISARIYA, SHAILENDRA, & SAXENA, MUDIT (2024). Design Analysis and Implementation of Two Stage Operational Amplifier. International Journal of Advance Research and Innovative Ideas In Education, 10(3), 4210-4217.

MLA Style

KESARWANI, RAJ, et al. "Design Analysis and Implementation of Two Stage Operational Amplifier." International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 3, 2024, pp. 4210-4217.

IEEE Style

RAJ KESARWANI, RAHUL PANDEY, SAHIL AGARWAL, SHAILENDRA BISARIYA, and MUDIT SAXENA, "Design Analysis and Implementation of Two Stage Operational Amplifier," International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 3, pp. 4210-4217, 2024.

Vancouver Style

KESARWANI RAJ, PANDEY RAHUL, AGARWAL SAHIL, BISARIYA SHAILENDRA, SAXENA MUDIT. Design Analysis and Implementation of Two Stage Operational Amplifier. International Journal of Advance Research and Innovative Ideas In Education. 2024;10(3):4210-4217.

Harvard Style

KESARWANI, RAJ, PANDEY, RAHUL, AGARWAL, SAHIL, BISARIYA, SHAILENDRA, & SAXENA, MUDIT (2024) 'Design Analysis and Implementation of Two Stage Operational Amplifier', International Journal of Advance Research and Innovative Ideas In Education, 10(3), pp. 4210-4217.

Chicago Style

KESARWANI, RAJ, et al. "Design Analysis and Implementation of Two Stage Operational Amplifier." International Journal of Advance Research and Innovative Ideas In Education 10, no. 3 (2024): 4210-4217.

Turabian Style

KESARWANI, RAJ, et al. "Design Analysis and Implementation of Two Stage Operational Amplifier." International Journal of Advance Research and Innovative Ideas In Education 10, no. 3 (2024): 4210-4217.