1X3 ROUTER RTL & UVM TESTBENCH

MOHARIL ABOLI; SINGH UTKARSH DINESH; RAORANE KRUNAL VIJAY; YADAV PRADEEP JANGBAHADUR; YADAV DURGESH AMARJEET

1X3 ROUTER RTL & UVM TESTBENCH

April 2023

Vol-9, Issue-2

Paper ID: 19849

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronic and Telecommunication (VLSI BASED)

Keywords

Router Top Model FSM FIFO REG SYNC XILINX ISIM RTL UVM

Abstract

Abstract: This technical paper presents the design and implementation of a router using Verilog RTL. The router is capable of routing data packets from a source network to three different client networks. The design includes a register module to hold data packets momentarily and pass them on to three different First-In-First-Out (FIFO) memories, a Finite State Machine (FSM) module, and a Synchronizer module to manipulate internal signals for efficient task execution. The project was simulated using Xilinx ISE and ISIM, with code coverage analysis performed on Questa Sim. The RTL was verified through a Test Bench in a UVM-based environment. The router module was implemented using 130nm technology, with a packet width of 8 bits and a maximum packet length of 63 bytes. The top-level design and sub-modules were described, and the simulation and verification processes were detailed. The results showed that the FSM with a reduced number of states resulted in improved frequency response. The design can be extended to handle larger packet sizes and more client networks. This router implementation can be used in various networking applications, including the internet of things (IoT), industrial automation, and telecommunications.

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Author Information

#	Name	Institute / Affiliation
1	MOHARIL ABOLI	Shree L.R. Tiwari College Of Engineering
2	SINGH UTKARSH DINESH	Shree L.R. Tiwari College Of Engineering
3	RAORANE KRUNAL VIJAY	Shree L.R. Tiwari College Of Engineering
4	YADAV PRADEEP JANGBAHADUR	Shree L.R. Tiwari College Of Engineering
5	YADAV DURGESH AMARJEET	Shree L.R. Tiwari College Of Engineering

How to Cite

Use the following formats to cite this article in your research.

APA Style

ABOLI, MOHARIL, DINESH, SINGH UTKARSH, VIJAY, RAORANE KRUNAL, JANGBAHADUR, YADAV PRADEEP, & AMARJEET, YADAV DURGESH (2023). 1X3 ROUTER RTL & UVM TESTBENCH. International Journal of Advance Research and Innovative Ideas In Education, 9(2), 2465-2471.

MLA Style

ABOLI, MOHARIL, et al. "1X3 ROUTER RTL & UVM TESTBENCH." International Journal of Advance Research and Innovative Ideas In Education, vol. 9, no. 2, 2023, pp. 2465-2471.

IEEE Style

MOHARIL ABOLI, SINGH UTKARSH DINESH, RAORANE KRUNAL VIJAY, YADAV PRADEEP JANGBAHADUR, and YADAV DURGESH AMARJEET, "1X3 ROUTER RTL & UVM TESTBENCH," International Journal of Advance Research and Innovative Ideas In Education, vol. 9, no. 2, pp. 2465-2471, 2023.

Vancouver Style

ABOLI MOHARIL, DINESH SINGH UTKARSH, VIJAY RAORANE KRUNAL, JANGBAHADUR YADAV PRADEEP, AMARJEET YADAV DURGESH. 1X3 ROUTER RTL & UVM TESTBENCH. International Journal of Advance Research and Innovative Ideas In Education. 2023;9(2):2465-2471.

Harvard Style

ABOLI, MOHARIL, DINESH, SINGH UTKARSH, VIJAY, RAORANE KRUNAL, JANGBAHADUR, YADAV PRADEEP, & AMARJEET, YADAV DURGESH (2023) '1X3 ROUTER RTL & UVM TESTBENCH', International Journal of Advance Research and Innovative Ideas In Education, 9(2), pp. 2465-2471.

Chicago Style

ABOLI, MOHARIL, et al. "1X3 ROUTER RTL & UVM TESTBENCH." International Journal of Advance Research and Innovative Ideas In Education 9, no. 2 (2023): 2465-2471.

Turabian Style

ABOLI, MOHARIL, et al. "1X3 ROUTER RTL & UVM TESTBENCH." International Journal of Advance Research and Innovative Ideas In Education 9, no. 2 (2023): 2465-2471.