ANALYSIS AND DESIGN OF THREE PHASE MULTI-LEVEL INVERTER WITH REDUCED NUMBER OF SWITCHES

electrical engineering

A multilevel inverter for generating multiple voltage levels using a series-parallel connection of modules with intermediate power source has been proposed. As compared to conventional inverter topologies like diode clamped and capacitor clamped inverters, the cascaded multilevel inverter has lesser harmonics as well as lower switching stress. The cascaded topology has more number of power switches leading to greater heat losses, larger size, higher cost and more gate drive circuitry. The proposed configuration contains less number of switches and produces lesser harmonics in the output voltage than the cascaded topology. To analyze the performance of the proposed circuit SPWM technique has used. The results have been verified through simulation study in MATLAB/Simulink in order to select the best PWM method that provides minimum THD in the output voltage. An LC filter has been designed to improve the harmonic profile

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