Analytical Sizing and Layout of a High-Gain CMOS Comparator for Mixed-Signal Applications

Engineering

High-speed and high-resolution analog-to-digital converters (ADCs) impose stringent performance requirements on their core decision-making blocks, especially the comparator. As the fundamental building element of ADCs, the comparator effectively behaves as a 1 bit analog-to-digital converter and strongly influences the overall speed and accuracy of the system. This paper presents the design, systematic sizing procedure, and physical layout implementation of a high-gain, two-stage, open-loop CMOS comparator operating from a symmetric ±2.5 V power supply. The circuit architecture is optimized to maximize the output slew rate while driving a heavy capacitive load of up to 5 pF, under given specifications on DC open-loop gain, propagation delay, and input common-mode range (ICMR). Theoretical design equations used for device dimensioning are validated through simulations using industry-standard EDA tools. The verification results confirm that the designed comparator achieves a DC open-loop gain greater than 10 000 V/V, a propagation delay of approximately 50 ns, and a wide ICMR extending from −1.25V to 2.5 V, while maintaining full-swing output levels. Furthermore, a highly symmetric layout structure is employed to mitigate device mismatch, ensuring robust and stable performance for mixed-signal integrated circuit applications.

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