Design and analysis of 6T SRAM cell using FINFET at Nanometer Regime

VLSI

With the scaling of MOSFET there is a increase in the channel length modulation, Drain induced barrier lowering (DIBL), increase in sub threshold slope and gate leakage all these effects decreases gate coupling to the channel. FINFET technology is one alternative which can offer the performance as may be expected from next generation Si technology. FINFET is expected to replace conventional MOSFETs and also SOI MOSFET for integrated memory applications due to better resistant to some of the source of intrinsic parameter fluctuation. We can improve the performance of 6T SRAM using FINFET. Chip density increases due to smaller transistor dimensions. The stability of SRAM cell affected due to the nano technology nodes variation in Process, voltage, and Temperature (PVT). In the proposed work 6T SRAM is implemented using 32 nm Bulk MOSFET and FINFET and stability in hold/standby, read and Write mode is ananlysed. Design consider Bulk MOSFET, SOI MOSFET and FINFET at 32nm technological node. The working and stability of 6T SRAM in all modes of operation has been analyzed. Supply voltage, temperature, transistor scaling of Bulk MOSFET, SOI MOSFET and FINFET are analyzed during read and standby mode. A comparative study between Bulk 6T SRAM and SOI 6T SRAM and FINFET 6TSRAM has been made in this work. For this work we have use 32 nm FINFET and 32nm Bulk MOSFET PTM file, and all the simulation work is carried out in HSPICE 2008.3

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