FPGA Based Implementation of UART bus for AES Algorithm

Mayank M. Bhanani; Prof. Deepak R. Parashar

FPGA Based Implementation of UART bus for AES Algorithm

May 2016

Vol-2, Issue-3

Paper ID: 2425

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronics

Keywords

asynchronous serial communication VHDL Quartus II simulation DE1 board

Abstract

UART (Universal Asynchronous Receiver Transmitter) is a serial communication bus which mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. Here in this paper we are going to implement UART on the FPGA board (Altera DE1 – EP2C20F484C7). The synthesis and simulation is done on the licensed Altera Quartus II 6.0 web addition. Whole coding is done in the VHDL language and implemented on FPGA to achieve compact, stable and reliable data transmission.

License

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author Information

#	Name	Institute / Affiliation
1	Mayank M. Bhanani	PG Scholar, Electronic & Communication Department, G.H. Patel Engineering College, Anand, India
2	Prof. Deepak R. Parashar	Professor, Electronic& Communication Department, G.H. Patel Engineering College, Anand, India

How to Cite

Use the following formats to cite this article in your research.

APA Style

Bhanani, Mayank M. & Parashar, Prof. Deepak R. (2016). FPGA Based Implementation of UART bus for AES Algorithm. International Journal of Advance Research and Innovative Ideas In Education, 2(3), 3144-3148.

MLA Style

Bhanani, Mayank M., and Prof. Deepak R. Parashar. "FPGA Based Implementation of UART bus for AES Algorithm." International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, 2016, pp. 3144-3148.

IEEE Style

Mayank M. Bhanani and Prof. Deepak R. Parashar, "FPGA Based Implementation of UART bus for AES Algorithm," International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, pp. 3144-3148, 2016.

Vancouver Style

Bhanani Mayank M., Parashar Prof. Deepak R.. FPGA Based Implementation of UART bus for AES Algorithm. International Journal of Advance Research and Innovative Ideas In Education. 2016;2(3):3144-3148.

Harvard Style

Bhanani, Mayank M. & Parashar, Prof. Deepak R. (2016) 'FPGA Based Implementation of UART bus for AES Algorithm', International Journal of Advance Research and Innovative Ideas In Education, 2(3), pp. 3144-3148.

Chicago Style

Bhanani, Mayank M. and Prof. Deepak R. Parashar. "FPGA Based Implementation of UART bus for AES Algorithm." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 3144-3148.

Turabian Style

Bhanani, Mayank M. and Prof. Deepak R. Parashar. "FPGA Based Implementation of UART bus for AES Algorithm." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 3144-3148.