8-BIT SAR ADC USING COUNTER-BASED DIGITAL CONTROL CIRCUIT IN 90NM CMOS TECHNOLOGY

Electronics Engineering

The conventional 8-bit SAR ADCs that use conventional Control Circuit consume more power, have more delay, and take up more area. In terms of area, power savings, and delay, approximate 8-bit SAR ADCs using CBDCC are far better. Instead of binary search resistive ladder network we used a charge-redistribution capacitor array DAC in this. Traditional SAR based ADC are not suitable for biosensor application, operating at very low frequency due to it is more power requirement in fault tolerant application. To meet low power requirement CBDCC is implemented in Cadence virtuoso environment using 90nm CMOS Technology to evaluate the power consumption, critical path delay. An 8-bit SAR ADC using CBDCC is designed using the D-FFs and 4-i/p clock-gated AND gates. A double-tail latch type comparator has been integrated into the design to reduce power consumption and increase speed. For charge redistribution DAC, area efficiency and for faster operation, synchronous type SAR logic with a counter-based controlled unit is proposed. 90 nm CMOS technology was used to design and simulate the structure. The design is divided into several blocks, which are individually implemented and tested at 10K samples/s and 1V power supply. The SAR-ADC consumed 252.5µW. The results show that the proposed SAR-ADC in 90 nm technology is a good candidate for biomedical medical application.

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