Fast FPGA Routing Approach Using Stochestic Architecture

VLSI SYSTEM DESIGN

In this thesis I am going to reconfigure the hardware and connect each an every block in FPGA for improve FPGA performance much faster and try to overcome power consumption issue using Stochestic Architecture. In this Architecture will connect each un-routed blocks , by providing nearest routing path related to the CLB configuration .For this configuration use wire or microcell over these connection, so it perform much accurate and remove un-wanted connections inside the Routing connection. Design Fast FPGA performance, so I want to make Routing connection maximum shortest path and connect all switch or block connection using Cross-bar Algorithm, so make routing more accurate, improve connection of block ratio, reduce area, Time, power according to the configuration .I try to reduce clock delay and frequency, so ultimately performance of FPGA also increase and perform much faster, and finally Dump on FPGA Hardware.

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