An Approach to FinFET USING Ternary  logic

Kushawaha Jyoti Dineshkumar; Abhinav Singh; Bhavit Rathore

An Approach to FinFET USING Ternary logic

May 2016

Vol-2, Issue-3

Paper ID: 2173

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

VLSI System Design

Keywords

FinFET CMOS ALU Ternary logic.

Abstract

Ternary Logic is advantageous choice to substitute binary logic as it is energy efficient and due to easiness, as interconnect and chip area are reduced. As CMOS technology is scaling down to nanometer regime there are many problems occurring such as short channel effect, DIBL and Hot electron Effect, these problems can be overcomed by replacing traditional CMOS by FinFET. These two methodologies are of great advantage and can result in new turn in nanoelectronics. Many circuits can be build up by using FinFET working on ternary logic rather than binary and the main is ALU as it is the heart of CPU. So designing circuits by these two methodologies has a great impact on upcoming technologies.

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Author Information

#	Name	Institute / Affiliation
1	Kushawaha Jyoti Dineshkumar	Gtu Pg School, Ahmedabad, Gujarat
2	Abhinav Singh	Veltech Technical University, Chennai
3	Bhavit Rathore	Veltech Technical University, Chennai

How to Cite

Use the following formats to cite this article in your research.

APA Style

Dineshkumar, Kushawaha Jyoti, Singh, Abhinav, & Rathore, Bhavit (2016). An Approach to FinFET USING Ternary logic. International Journal of Advance Research and Innovative Ideas In Education, 2(3), 421-425.

MLA Style

Dineshkumar, Kushawaha Jyoti, et al. "An Approach to FinFET USING Ternary logic." International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, 2016, pp. 421-425.

IEEE Style

Kushawaha Jyoti Dineshkumar, Abhinav Singh, and Bhavit Rathore, "An Approach to FinFET USING Ternary logic," International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, pp. 421-425, 2016.

Vancouver Style

Dineshkumar Kushawaha Jyoti, Singh Abhinav, Rathore Bhavit. An Approach to FinFET USING Ternary logic. International Journal of Advance Research and Innovative Ideas In Education. 2016;2(3):421-425.

Harvard Style

Dineshkumar, Kushawaha Jyoti, Singh, Abhinav, & Rathore, Bhavit (2016) 'An Approach to FinFET USING Ternary logic', International Journal of Advance Research and Innovative Ideas In Education, 2(3), pp. 421-425.

Chicago Style

Dineshkumar, Kushawaha Jyoti, Abhinav Singh, and Bhavit Rathore. "An Approach to FinFET USING Ternary logic." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 421-425.

Turabian Style

Dineshkumar, Kushawaha Jyoti, Abhinav Singh, and Bhavit Rathore. "An Approach to FinFET USING Ternary logic." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 421-425.