Device design Methodology to optimize low frequency noise in SOI Technology

Silicon on Insulator

Device design methodology for SOI is to improve power and reduce low frequency noise generated randomly. An effort to reduce the power consumption of the circuit, the supply voltage can be reduced leading to reduction of dynamic and static power consumption. SOI introduces one of the greatest future generation technologies of this decade. Silicon-on-Insulator transistors are fabricated in a small ~100 nm layer of silicon, located on top of a silicon dioxide layer, called buried oxide. This oxide layer provides full dielectric isolation of the transistor and thus most of the parasitic effects present in bulk silicon transistors are eliminated. The structure of the SOI transistor is depicted and is very similar to that of the bulk transistor. The main difference is the presence of the buried oxide it provides attractive properties to the SOI transistor. Power has become one of the most important paradigms of design convergence for multi gigahertz communication such as optical data links wireless products and microprocessor ASIC or SOC designs. Power consumption has become bottleneck in microprocessor design.

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