Reconfigurable Hardware for ZUC stream cipher

VLSI and Embedded

In the world of cryptography, stream ciphers are known as primitives used to ensure privacy over a communication channel. One common way to build a stream cipher is to use a keystream generator to produce a pseudorandom sequence of symbols. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offering reliable security services in Long Term Evolution networks (LTE), which is a candidate standard for the 4G network. A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. Stream ciphers are more efficient when implemented in hardware environment, like Field Programmable Gate Array (FPGA). The design is coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA is used. In this paper a reconfigurable implementation of ZUC stream cipher using Carry Look Ahead Adder is presented. This achieved a throughput of 3.2180 Gbps.

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