Advance Techniques for Lower Power Digital VLSI

Divya Kanuganti; Dr. Anil Kumar

Advance Techniques for Lower Power Digital VLSI

January 2021

Vol-4, Issue-2

Paper ID: 13448

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronics

Keywords

Power Digital VLSI Semiconductor PMOS NMOS.

Abstract

The principle point of this examination is to talk about the Lower Power Digital VLSI Using High Speed SRAM, To improve the plan limitations: strength, speed, spillage current and postpone which impacts the presentation of SRAM cell and besides presents the various procedures, find better arrangement through Simulation done on different SRAM cell, explore the Low Power SRAM Cell geographies on 65 nm development by using various boundaries and to assess the usage of MTCMOS Technique on Conventional and Ground–Gated SRAM cell geographies. The principle objective of our own will be keeping up execution of psyche cell continuously activity. The working of SRAM will be impacted by extraneous and inherent boundaries. Now, we'll be focusing on essential 3 boundaries: dependability, spillage current and deferral.

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Author Information

#	Name	Institute / Affiliation
1	Divya Kanuganti	Research Scholar of Sri Satya Sai University
2	Dr. Anil Kumar	Research Supervisor of Sri Satya Sai University

How to Cite

Use the following formats to cite this article in your research.

APA Style

Kanuganti, Divya & Kumar, Dr. Anil (2021). Advance Techniques for Lower Power Digital VLSI. International Journal of Advance Research and Innovative Ideas In Education, 4(2), 4934-4938.

MLA Style

Kanuganti, Divya, and Dr. Anil Kumar. "Advance Techniques for Lower Power Digital VLSI." International Journal of Advance Research and Innovative Ideas In Education, vol. 4, no. 2, 2021, pp. 4934-4938.

IEEE Style

Divya Kanuganti and Dr. Anil Kumar, "Advance Techniques for Lower Power Digital VLSI," International Journal of Advance Research and Innovative Ideas In Education, vol. 4, no. 2, pp. 4934-4938, 2021.

Vancouver Style

Kanuganti Divya, Kumar Dr. Anil. Advance Techniques for Lower Power Digital VLSI. International Journal of Advance Research and Innovative Ideas In Education. 2021;4(2):4934-4938.

Harvard Style

Kanuganti, Divya & Kumar, Dr. Anil (2021) 'Advance Techniques for Lower Power Digital VLSI', International Journal of Advance Research and Innovative Ideas In Education, 4(2), pp. 4934-4938.

Chicago Style

Kanuganti, Divya and Dr. Anil Kumar. "Advance Techniques for Lower Power Digital VLSI." International Journal of Advance Research and Innovative Ideas In Education 4, no. 2 (2021): 4934-4938.

Turabian Style

Kanuganti, Divya and Dr. Anil Kumar. "Advance Techniques for Lower Power Digital VLSI." International Journal of Advance Research and Innovative Ideas In Education 4, no. 2 (2021): 4934-4938.