AN EFFICIENT VLSI ARCHITECTURE FOR IMAGE COMPRESSION USING DWT TECHNIQUE

Electronics and Communication Engineering

The modern real time applications related to image processing demand high performance discrete wavelet transform (DWT). The proposed architecture includes Line Buffers, PIPO and Lifting Block. This architecture works in non-separable fashion using a lifting scheme computes 1D, 2D and 3D-DWT at different resolution levels. The lifting scheme represents the fastest implementation of the DWT than the existing convolution based DWT. The proposed 3D-DWT achieves reduction in total area and net power respectively as compared with existing convolution DWT. The major objective of this work is to improve the performance of the DWT for DSP applications. The experimental results shows the proposed design requires less delay, area, and power dissipation than existing systems.

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