AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT

S.RINI SANZES; P.PRIYADHARSHINI; M.SHALINI

AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT

March 2019

Vol-5, Issue-2

Paper ID: 9750

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

ELECTRONICS AND COMMUNICATION ENGINEERING

Keywords

Fast Fourier Transform(FFT) Fused Dot Product(FDP) Fused Add-Subtract(FAS)

Abstract

The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal. Some of the application of the Fast Fourier Transform include Signal analysis, Data compression, Partial differential equation, Multiplication of larges integers etc.,. The FFT can be designed by radix-4 butterfly algorithm which requires needless computations and data storage. The presenting the design and simulation of a 32 bit floating point FFT processor. In our proposed method we used concept of normal Booth encoding algorithm and designed a new DADDA algorithm which can be reduced area. The proposed design is to be implemented for single precision and will be synthesized with 90nm standard cell library. The proposed design fused dot product and fused add /subtract unit take four normalized operands and compute the sum and difference as (AB ± CD) respectively. Experiment result shows that the proposed floating point FDP and FAS unit by VLSI gives high speed, low area hardware floating point FDP and FAS unit.

License

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Author Information

#	Name	Institute / Affiliation
1	S.RINI SANZES	PRINCE SHRI VENKATESHWARA PADMAVATHY ENIGNEERING COLLEGE
2	P.PRIYADHARSHINI	PRINCE SHRI VENKATESHWARA PADMAVATHY ENIGNEERING COLLEGE
3	M.SHALINI	PRINCE SHRI VENKATESHWARA PADMAVATHY ENIGNEERING COLLEGE

How to Cite

Use the following formats to cite this article in your research.

APA Style

SANZES, S.RINI, P.PRIYADHARSHINI, & M.SHALINI (2019). AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT. International Journal of Advance Research and Innovative Ideas In Education, 5(2), 807-812.

MLA Style

SANZES, S.RINI, et al. "AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT." International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, 2019, pp. 807-812.

IEEE Style

S.RINI SANZES, P.PRIYADHARSHINI, and M.SHALINI, "AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT," International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, pp. 807-812, 2019.

Vancouver Style

SANZES S.RINI, P.PRIYADHARSHINI, M.SHALINI. AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT. International Journal of Advance Research and Innovative Ideas In Education. 2019;5(2):807-812.

Harvard Style

SANZES, S.RINI, P.PRIYADHARSHINI, & M.SHALINI (2019) 'AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT', International Journal of Advance Research and Innovative Ideas In Education, 5(2), pp. 807-812.

Chicago Style

SANZES, S.RINI, P.PRIYADHARSHINI, and M.SHALINI. "AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 807-812.

Turabian Style

SANZES, S.RINI, P.PRIYADHARSHINI, and M.SHALINI. "AN AREA EFFICIENT AND HIGH SPEED PROCESSOR FOR FLOATING POINT FUSED DOT PRODUCT AND FUSED ADD-SUBTRACT FOR FFT." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 807-812.