Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication

Shekar.R; Vigneshwaran.D

Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication

March 2019

Vol-5, Issue-2

Paper ID: 9734

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronics and Communication Engineering

Keywords

Vedic real multiplier Urdhva Triyakbhyam sutra complex multiplier FPGA area efficient architecture array multiplier

Abstract

In this paper, an area reduced multiplier design is conferred. This structure is based on ancient algorithm of Vedas, proposed within the Vedic mathematics scripture of Sri Bharati Krshna Tirthai Maharaja. Complex number multiplication is a very important numerical operation to be performed with fast and less power utilization in frameworks like Digital Signal Processing. Hence in this paper, a design is proposed for a vedic real multiplier based on urdhva tiryakbhyam sutra of Indian Vedic mathematics. The partial product and also sums are produced in few stages that decreases the carry propagation from LSB to MSB. In the proposed design we have reduced the amount of logic gates (area), hence reducing the power consumed. Finally, the effect of the Vedic multiplication is contrasted with array multiplication.

License

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author Information

#	Name	Institute / Affiliation
1	Shekar.R	Prince Shri Venkateshwara Padmavathy Engineering College
2	Vigneshwaran.D	Prince Shri Venkateshwara Padmavathy Engineering College

How to Cite

Use the following formats to cite this article in your research.

APA Style

Shekar.R & Vigneshwaran.D (2019). Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication. International Journal of Advance Research and Innovative Ideas In Education, 5(2), 882-885.

MLA Style

Shekar.R, and Vigneshwaran.D. "Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication." International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, 2019, pp. 882-885.

IEEE Style

Shekar.R and Vigneshwaran.D, "Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication," International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, pp. 882-885, 2019.

Vancouver Style

Shekar.R, Vigneshwaran.D. Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication. International Journal of Advance Research and Innovative Ideas In Education. 2019;5(2):882-885.

Harvard Style

Shekar.R & Vigneshwaran.D (2019) 'Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication', International Journal of Advance Research and Innovative Ideas In Education, 5(2), pp. 882-885.

Chicago Style

Shekar.R and Vigneshwaran.D. "Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 882-885.

Turabian Style

Shekar.R and Vigneshwaran.D. "Design of Area Efficient Complex Number Multiplier Using Vedic Multiplication." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 882-885.