PERFORMANCE ANALYSIS OF PULSED LATCH BASED SHIFT REGISTER

Electronics and Communication Engineering

The implementation of shift register using pulsed latches instead of flip flops is discussed in this paper. For designing the latch, Static Differential Sense Amplification Shared Pulsed Latch (SSASPL) is used along with Multi-threshold Complementary Metal Oxide Semiconductor (MTCMOS) to avoid the subthreshold leakage. Pulsed latch requires less area and power because it is smaller than the flip flop. But the pulsed latch cannot be used because timing problem occurs between pulsed latches. This is overcome by using multiple non-overlap delayed pulsed clock signals. Five non-overlap delayed pulsed clock signals are generated by the delayed pulsed clock generator. In the proposed shift register minimum number of the pulsed clock signals are used by grouping more number of sub shifter registers and using additional short-term storage latches. The AND and NOT gate in the pulser circuit are designed using GDI (Gate Diffusion Input) technique, to reduce the number of transistors used in the design. The design is simulated in Tanner EDA and the results obtained are in such a way that, the area and power consumption are reduced.

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