DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION

JANANI.R; JAYASHREE.V

DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION

March 2019

Vol-5, Issue-2

Paper ID: 9699

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

ELECTRONICS AND COMMUNICATION ENGINEERING

Keywords

DCT image compression Loeffler algorithm reduced delay low error DCT pipelining.

Abstract

In today’s life, multimedia is a major application for most of the image/video processing. In addition to that, the main source of image processing system can be obtained using Discrete Cosine Transform (DCT).This low error DCT can be effectively attained using registers as D flip flop for enhancing pipelining technique. Thus produces relatively less processing time and efficient memory usage.

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Author Information

#	Name	Institute / Affiliation
1	JANANI.R	PRINCE SHRI VENKATESHWARA PADMAVATHY ENGINEERING COLLEGE
2	JAYASHREE.V	PRINCE SHRI VENKATESHWARA PADMAVATHY ENGINEERING COLLEGE

How to Cite

Use the following formats to cite this article in your research.

APA Style

JANANI.R & JAYASHREE.V (2019). DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION. International Journal of Advance Research and Innovative Ideas In Education, 5(2), 640-649.

MLA Style

JANANI.R, and JAYASHREE.V. "DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION." International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, 2019, pp. 640-649.

IEEE Style

JANANI.R and JAYASHREE.V, "DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION," International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, pp. 640-649, 2019.

Vancouver Style

JANANI.R, JAYASHREE.V. DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION. International Journal of Advance Research and Innovative Ideas In Education. 2019;5(2):640-649.

Harvard Style

JANANI.R & JAYASHREE.V (2019) 'DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION', International Journal of Advance Research and Innovative Ideas In Education, 5(2), pp. 640-649.

Chicago Style

JANANI.R and JAYASHREE.V. "DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 640-649.

Turabian Style

JANANI.R and JAYASHREE.V. "DESIGN OF REDUCED DELAY AND EFFICIENT 2D DCT ARCHITECTURE FOR IMAGE COMPRESSION." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 640-649.