A hardware efficient pseudorandom generation using geffe generator

Electronics and Communication Engineering

The increasing complexity of VLSI circuits necessitates Nano scale device miniaturization as well as an intricate manufacturing process for their fabrication. This, however, has led to greater process variation and higher probability of defects and, consequently, has worsened yield. Various ATPG tools available today employ powerful heuristics and are capable of generating efficient and compact test sets for a circuit-under-test (CUT) .A new test-data compression method suitable for cores of unknown structure is introduced in this paper. The proposed method encodes the test data provided by the core vendor using a new, very effective compression scheme based on multilevel Huffman coding. Each Huffman code word corresponds to three different kinds of information, and thus, significant compression improvements compared to the already known techniques are achieved. In this project propose a testing methodology for the scan-based BIST (Built-in-self-test). Geffe generator and Huffman encoder is included in the test pattern generator (TPG) to reduce average power consumption during scan testing, while a group-based selection algorithm is employed for the scan-chain reorder in order to improve the fault coverage. The objective is to produce Test Pattern with good randomness; then fault coverage will be better. Fault simulation is done using Xilinx simulator.

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