A SURVEY PAPER ON PERFORMANCE ANALYSIS OF VEDIC MULTIPLICATION TECHNIQUE USING FPGA

Electronics and Telecommunication

Today, it is necessary to increase the speed of multiplier as the need of high speed processors is increasing. Multiplier is a main block of any processor. Conventional processors need great hardware resources and take more time in multiplication operation. This paper present a high speed multiplier based on ancient popular Vedic mathematics. Implementation is done on digital circuits. Vedic multiplication is accomplished in the same way as that of normal multiplier using digital hardware. In this paper a comparison of concerned multipliers in 8, 16 and 32bits multiplications is performed. 8 bit and 16bit urdhva algorithm shows 50% improvement in delay than that of nikhilam, whereas 100% better than that of binary multiplier. 32bit nikhilam multiplier gives 52% improvement in delay than that of urdhva multiplier and 16% better than that of binary multiplier. Multiplication is an important factor in arithmetic operations and is carried Out in variation of digital signal manage applications. As multipliers take a long time for execution so there is a need of fast multiplier to save the execution time. This paper describes the multiplication using ancient indian vedic mathematics multiplication techniques. Vedic mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 sutras. The techniques described in this paper are nikhilam sutra, urdhva tiryakbhyam and Karatsuba-of man and the performance analysis of these techniques is obtained. Modalism tool is used for simulation and the results obtained are compared on the basis of time delay of multiplication. This paper also describes the deliberateness and the fastness of different multiplier techniques Compared with each other.

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