IMPLEMENTATION OF HIGH SPEED MULTIPLIER USING VEDIC MATHEMATICS

Electronics and telecommunication engineering

Multipliers play a major role in processors and in many computational systems. The speed of these systems greatly depends on the speed of its multipliers. In order to enhance the speed of the systems the faster and efficient multipliers should be employed. Vedic Multiplier is one of the best solution which is capable of performing the quicker multiplications by eliminating the unwanted steps in the multiplication process. Power dissipation is another important constraint in an embedded system which cannot be neglected. The Reversible Logic has received great attention in the past recent years due to its ability in reducing the power dissipation, which is the major concern in Digital Designing. Here we present a high speed Vedic Multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra for multiplication from Vedic maths. It is a simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computation.

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