HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA

GAYATHRI K; HARSHINI V S; Dr SENTHIL KUMAR K K

HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA

March 2018

Vol-4, Issue-2

Paper ID: 7623

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

electronics and communication engineering

Keywords

Bitonic merge Bitonic odd even merge sort Comparator Bubble sort Parallelism Register transistor level Comparison Simulation. 4 bit 8 bit 16 bit 32 bit.

Abstract

Sorting is one of the most fundamental topics in computer science, It is the basic process in data analysis and in an enormous application.Software sorting doesn't provide efficiency so hardware sorting is used.In this proposed system the different hardware sorting is compared and the best sorting is justified.The register transfer level of each sorting is schematic by this paper.The model simulation also provided so, it is easy to compare the sorting.The bitonic merge sort and Bitonic odd even sort using parallelism concept are proposed in this paper

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Author Information

#	Name	Institute / Affiliation
1	GAYATHRI K	Prince Shri Venkateshwara Padmavathy Engineering College
2	HARSHINI V S	Prince Shri Venkateshwara Padmavathy Engineering College
3	Dr SENTHIL KUMAR K K	PRINCE SHRI VENKATESHWARA PADMAVATHY ENGINEERING COLLEGE

How to Cite

Use the following formats to cite this article in your research.

APA Style

K, GAYATHRI, S, HARSHINI V, & K, Dr SENTHIL KUMAR K (2018). HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA. International Journal of Advance Research and Innovative Ideas In Education, 4(2), 719-725.

MLA Style

K, GAYATHRI, et al. "HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA." International Journal of Advance Research and Innovative Ideas In Education, vol. 4, no. 2, 2018, pp. 719-725.

IEEE Style

GAYATHRI K, HARSHINI V S, and Dr SENTHIL KUMAR K K, "HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA," International Journal of Advance Research and Innovative Ideas In Education, vol. 4, no. 2, pp. 719-725, 2018.

Vancouver Style

K GAYATHRI, S HARSHINI V, K Dr SENTHIL KUMAR K. HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA. International Journal of Advance Research and Innovative Ideas In Education. 2018;4(2):719-725.

Harvard Style

K, GAYATHRI, S, HARSHINI V, & K, Dr SENTHIL KUMAR K (2018) 'HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA', International Journal of Advance Research and Innovative Ideas In Education, 4(2), pp. 719-725.

Chicago Style

K, GAYATHRI, HARSHINI V S, and Dr SENTHIL KUMAR K K. "HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA." International Journal of Advance Research and Innovative Ideas In Education 4, no. 2 (2018): 719-725.

Turabian Style

K, GAYATHRI, HARSHINI V S, and Dr SENTHIL KUMAR K K. "HARDWARE IMPLEMENTATION OF SORTING ALGORITHM USING FPGA." International Journal of Advance Research and Innovative Ideas In Education 4, no. 2 (2018): 719-725.