A REVIEW : AXI BUS INTERFACING BETWEEN FPGA AND HPS IN MSS HUB NETWORK

Electronics and Communication Engineering

In MSS (mobile satellite services) services there are different products that we are using like SGU (satellite gateway unit), VGU (voice gateway unit), TGU (traffic gateway unit) so on. These different products are based on rabbit processor technology. For advanced hub (MSS), this product needs to be optimized for a high speed on FPGA devices. In SOC FPGA, input is ethernet data (TCP/IP) and output can be serial data, HDLC data or some data conversion. In SOC FPGA, LAN/IP stack, serial data is handled by the Arm processor and protocol conversion in HDLC and compute intensive tasks can be done in parallel, pipelined fashion in FPGA to transfer high speed ethernet traffic in a SOC/FPGA. To route ethernet traffic from Arm processor to FPGA and vice versa AXI interface is used that gives high speed. We have a AXI master on HPS side, so to connect FPGA, QSYS will automatically connect adapters of AXI slave and MM master that consumes most of the logic elements and reduces the speed of transfer. So, I will make AXI slave on FPGA side that will solve this both the problems.

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