Speed Efficient 64 Bit MAC Design using VEDIC Multiplier and Reversible Logic Gates

electronics and communication engineering

A multiplying block operate may be concededin 3 totally different ways: standard addition, partial product addition (PPA) and eventually partial product Generation (PPG).The two bud vase materials that must be considered are raising the speed of MAC which is accumulator block partial and product reduction. The 64 bit MAC design which will make use of Vedic multiplier and reversible logic gate can be accomplished in two stages. Firstly, multiplier stage, where a usual multiplier is replaced by Vedic multiplier using UrdhavaTriyagbhayam sutra from Vedic Mathematics. Multiplication is the primary operation of MAC unit. Speed, area, Power dissipation, consumption and latency are the major concerns in the multiplier stage. So, to evade them, we are going to select quick multipliers innumerous applications of DSP, networking, etc.

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