SPLIT - RADIX FFT PROCESSORS WITH LOW - POWER USING CARRY SELECT

ELECTRONICS AND COMMUNICATION ENGINEERING

Split-Radix Fast Fourier Transform (SRFFT) is mainly for the implementation of a low-power FFT processor. In FFT algorithms, SRFFT has less number of arithmetic operations. Twiddle factor is required in FFT addressing processors. The signal flow graph of SRFFT is the same as radix-2 FFT and so conventional addressing schemes is used in of SRFFT. However, it has improper arrangement of twiddle factors and denies application of radix-2 address generation methods.This brief presents a shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by using a butterfly unit. The butterfly unit exploits the multiplier-gating technique to save dynamic power. In addition, two novel address generation algorithm for both trivial and non-trivial twiddle factors are developed. The proposed design achieves over a less delay, higher speed and 20% dynamic low power consumption.

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