DESIGN OF HIGH PERFORMANCE, AREA EFFICIENT FIR FILTER USING CARRY SELECT ADDER

Electronics and Communication Engineering

Adders are the most widely used components in many data-processing processors to perform arithmetic functions. Carry Select Adder (CSLA) is known to be the fastest adder among the conventional adder structures. The main advantage of CSLA is its reduced propagation delay characteristics with increase in area .The area of the CSLA will be reduced by using a simple and efficient gate-level modification. The basic idea is to use Binary to Excess-1 Converter (BEC) instead of RCA with cin=1 in the regular CSLA to achieve lower area .The main advantage of this BEC logic comes from the lesser number of logic gates than the n-bit Full Adder (FA) structure. Based on this modification 4,7,11 and 16 bit square-root CSLA (SQRT CSLA) architecture will be developed and compared with the regular SQRT CSLA and ripple carry adder architecture. The proposed design will reduce the area & delay as compared with the regular SQRT CSLA. Analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. The high performance & area efficient carry select adder has been implemented in the design of FIR filter to improve the performance of filter.

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.