A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK

Kashish Bhargava; Prashant Singodiya

A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK

April 2017

Vol-3, Issue-2

Paper ID: 4577

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

ECE

Keywords

LVDS FPGA Design Data Rates Speed Signal etc.

Abstract

In this paper we are presenting a review of multi lane LVDS inter FPGA communication link. In this paper we are main focus of LVDS and FPGA communication link. This paper describes a review of a multi-lane Low Voltage Differential Signaling (LVDS) interface to form 10 Gbps full duplex communication link interconnecting multiple FPGAs on a board. We also developed a Bit Error Rate Tester for evaluating each individual LVDS physical lane operating at 625 Mbps. Data rates of more than 455 Gbits/s inchips can be achieved using LVDS interface technique. As Integrated Circuit’s communication speeds has increased differential signalling is used to handle high speed. Design of high speed LVDS (Low Voltage Differential Signalling) bus interface controller using FPGA is presented. Source synchronous clocking is used to achieve this high speed data transfer.

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Author Information

#	Name	Institute / Affiliation
1	Kashish Bhargava	BHAGWANT UNIVERSITY
2	Prashant Singodiya	BHAGWANT UNIVERSITY

How to Cite

Use the following formats to cite this article in your research.

APA Style

Bhargava, Kashish & Singodiya, Prashant (2017). A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK. International Journal of Advance Research and Innovative Ideas In Education, 3(2), 3162-3165.

MLA Style

Bhargava, Kashish, and Prashant Singodiya. "A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK." International Journal of Advance Research and Innovative Ideas In Education, vol. 3, no. 2, 2017, pp. 3162-3165.

IEEE Style

Kashish Bhargava and Prashant Singodiya, "A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK," International Journal of Advance Research and Innovative Ideas In Education, vol. 3, no. 2, pp. 3162-3165, 2017.

Vancouver Style

Bhargava Kashish, Singodiya Prashant. A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK. International Journal of Advance Research and Innovative Ideas In Education. 2017;3(2):3162-3165.

Harvard Style

Bhargava, Kashish & Singodiya, Prashant (2017) 'A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK', International Journal of Advance Research and Innovative Ideas In Education, 3(2), pp. 3162-3165.

Chicago Style

Bhargava, Kashish and Prashant Singodiya. "A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK." International Journal of Advance Research and Innovative Ideas In Education 3, no. 2 (2017): 3162-3165.

Turabian Style

Bhargava, Kashish and Prashant Singodiya. "A REVIEW OF SPEED MULTI - LANE LVDS INTER – FPGA COMMUNICATION LINK." International Journal of Advance Research and Innovative Ideas In Education 3, no. 2 (2017): 3162-3165.