SPECULATIVE HAN-CARLSON ADDER FOR THE IMPROVEMENT OF SPEED OF CONVENTIONAL CARRY SKIP ADDER

ELECTRONICS ENGINEERING

This paper was designed to enhance the speed performance of the conventional carry skip adder. Many methods have already been designed for this purpose. One such method was the use of concatenation and incrementation scheme where the multiplexer logic was replaced by the And-Or-Invert (AOI) and Or-And-Invert (OAI) logic blocks. Also for further speed improvement the parallel prefix adder was introduced in the former system. This parallel prefix adder that was employed is the Brent Kung Adder. So, in this paper for further improving the speed, we make use of Speculative Han-Carlson Adder in place of Brent Kung Adder. Here, the adder can be implemented in both fixed stage size and variable stage size. The results were analyzed using Xilinx 13.2 software. The outcomes proved that Speculative Han-Carlson Adder showed a delay of 11.381ns which is less than that of Brent Kung Adder having a delay of 14.64ns.

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