Implementation of Optimized Low Power and Area Efficient MAC Unit for FIR Filter

Electronics and Communication Engineering

The Direct Form FIR filter is used for DSP application where the filter order is fixed. Generally this filter consumes more area and power. To overcome this problem Multiplier Control Signal Decision window (MCSD) schemes is incorporated into Direct Form FIR filter to dynamically change the filter order. MCSD structures consists of Control signal Generator (CG) and Amplitude Detection (AD) logic circuits. AD logic is used to revoke the right multiplication process and monitor the amplitudes of input samples. CG is used to control the filter operation through internal counter. Conventional reconfigurable FIR filter is designed using Vedic Multiplier that consumes more area and delay. In this paper, modified reconfigurable FIR filer is designed to further reduce the APT (Area, Power and Timing) product. The proposed Reconfigurable FIR filer, Vedic Multiplier is replaced by Russian Peasant Multiplication technique. Hence modified Reconfigurable FIR filter with Russian Peasant Multiplier consumes less area, delay and power than all compared methods.

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