FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD

Ms.C.Kowsalya; Mrs.S.Kalaivani

FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD

March 2017

Vol-3, Issue-2

Paper ID: 4073

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Power Electronics and Drives

Keywords

IGBT Gate drivers Multilevel inverter Hybrid level MATLAB/SIMULINK.

Abstract

Application of multilevel inverters for higher voltage goals in industries has become more popular. In this study, new structures for symmetric, asymmetric and hybrid multilevel inverter are recommended. The proposed structure is used in high-voltage levels. The proposed structure can generate a great number of voltage levels with minimum number of power electronic components such as Insulated Gate Bipolar Transistors (IGBT) and gate drivers. For proposed asymmetric and hybrid inverter, new methods for determination of DC voltage sources values are presented. Comparison of the results of various multilevel inverters is presented to reflect the merits of the recommended structures. The operations of the proposed multilevel inverter structures are verified with the experimental and simulation results of an asymmetric 31-level. Fundamental frequency-switching method is applied to the new topologies to trigger the power switches for controlling the voltage levels generated on the output. Verification of the analytical results is performed using MATLAB/SIMULINK software.

License

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author Information

#	Name	Institute / Affiliation
1	Ms.C.Kowsalya	Kathir College of Engineering
2	Mrs.S.Kalaivani	Kathir College of Engineering

How to Cite

Use the following formats to cite this article in your research.

APA Style

Ms.C.Kowsalya & Mrs.S.Kalaivani (2017). FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD. International Journal of Advance Research and Innovative Ideas In Education, 3(2), 651-658.

MLA Style

Ms.C.Kowsalya, and Mrs.S.Kalaivani. "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD." International Journal of Advance Research and Innovative Ideas In Education, vol. 3, no. 2, 2017, pp. 651-658.

IEEE Style

Ms.C.Kowsalya and Mrs.S.Kalaivani, "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD," International Journal of Advance Research and Innovative Ideas In Education, vol. 3, no. 2, pp. 651-658, 2017.

Vancouver Style

Ms.C.Kowsalya, Mrs.S.Kalaivani. FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD. International Journal of Advance Research and Innovative Ideas In Education. 2017;3(2):651-658.

Harvard Style

Ms.C.Kowsalya & Mrs.S.Kalaivani (2017) 'FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD', International Journal of Advance Research and Innovative Ideas In Education, 3(2), pp. 651-658.

Chicago Style

Ms.C.Kowsalya and Mrs.S.Kalaivani. "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD." International Journal of Advance Research and Innovative Ideas In Education 3, no. 2 (2017): 651-658.

Turabian Style

Ms.C.Kowsalya and Mrs.S.Kalaivani. "FPGA based implementation of new hybrid configuration 31 level inverter with reduced number of switches for reduced THD." International Journal of Advance Research and Innovative Ideas In Education 3, no. 2 (2017): 651-658.