ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER

K.BRINDHA DEVI; D.TAMILSELVI; K.SELVAPRIYA; S.KIRUTHIGA

ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER

February 2017

Vol-3, Issue-1

Paper ID: 3902

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

ELECTRONICS AND COMMUNICATION ENGINEERING

Keywords

Vedic Multiplier Urdhva Triyakbhyam Sutra Delay Carry skip technique Xilinx ….

Abstract

Multiplier plays an vital role in high performance of the system. Multiplication is the basic operation and the speed is limited by the adders used in the architecture. In this paper we have improved the processor speed there by reducing the delay. The speed of the processor is increased by one of the mathematical approach, Vedic mathematics. On the whole in Vedic mathematics Urdhva Triyakbhyam Sutra is used. Addition to this carry skip techniques is realized. An 8 bit multiplier is realized using 4 bit multiplier and thereby reducing the number of logic gates and delays. Simulation is carried out by using Xilinx software. Multipliers are mainly concentrated on speed, area and memory required.

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Author Information

#	Name	Institute / Affiliation
1	K.BRINDHA DEVI	VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN
2	D.TAMILSELVI	VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN
3	K.SELVAPRIYA	VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN
4	S.KIRUTHIGA	VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN

How to Cite

Use the following formats to cite this article in your research.

APA Style

DEVI, K.BRINDHA, D.TAMILSELVI, K.SELVAPRIYA, & S.KIRUTHIGA (2017). ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER. International Journal of Advance Research and Innovative Ideas In Education, 3(1), 1600-1607.

MLA Style

DEVI, K.BRINDHA, et al. "ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER." International Journal of Advance Research and Innovative Ideas In Education, vol. 3, no. 1, 2017, pp. 1600-1607.

IEEE Style

K.BRINDHA DEVI, D.TAMILSELVI, K.SELVAPRIYA, and S.KIRUTHIGA, "ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER," International Journal of Advance Research and Innovative Ideas In Education, vol. 3, no. 1, pp. 1600-1607, 2017.

Vancouver Style

DEVI K.BRINDHA, D.TAMILSELVI, K.SELVAPRIYA, S.KIRUTHIGA. ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER. International Journal of Advance Research and Innovative Ideas In Education. 2017;3(1):1600-1607.

Harvard Style

DEVI, K.BRINDHA, D.TAMILSELVI, K.SELVAPRIYA, & S.KIRUTHIGA (2017) 'ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER', International Journal of Advance Research and Innovative Ideas In Education, 3(1), pp. 1600-1607.

Chicago Style

DEVI, K.BRINDHA, et al. "ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER." International Journal of Advance Research and Innovative Ideas In Education 3, no. 1 (2017): 1600-1607.

Turabian Style

DEVI, K.BRINDHA, et al. "ANALYSIS AND DESIGN OF HIGH PERFORMANCE LOW POWER 8*8 VEDIC MULTIPLIER." International Journal of Advance Research and Innovative Ideas In Education 3, no. 1 (2017): 1600-1607.