Design and Implementation of a low power high speed full  adder cell for low power applications

Riya Srivastava; Vidhi Verma; Shivam Tiwari; Shailendra Bisariya; Mudit Saxena

Design and Implementation of a low power high speed full adder cell for low power applications

May 2024

Vol-10, Issue-3

Paper ID: 24108

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronics and Communication Engineering

Keywords

Conventional Adder CMOS Adder Full Adder Transmission Gate Full-adder Cell.

Abstract

An integral functional unit of every computational circuit, the one-bit full adder cell is one of the most commonly used digital circuit components in arithmetic logic units (ALUs). To date, a great deal of work has been done to enhance the architecture and functionality of complete adder circuit designs. This paper presents the implementation of two designs for 1-bit full adder cells at 90nm CMOS technology. One is conventional C-CMOS 1-bit adder cell and other one is Transmission Gate Logic (16-T) are used in 1-bit full adder cells. The proposed adder cells outperform the existing adder cells in terms of power consumption, delay, and power delay product (PDP), according to the simulation results comparing the proposed and existing adder cells.

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Author Information

#	Name	Institute / Affiliation
1	Riya Srivastava	ABES ENGINEERING COLLEGE, GHAZIABAD
2	Vidhi Verma	ABES ENGINEERING COLLEGE, GHAZIABAD
3	Shivam Tiwari	ABES ENGINEERING COLLEGE, GHAZIABAD
4	Shailendra Bisariya	ABES ENGINEERING COLLEGE, GHAZIABAD
5	Mudit Saxena	ABES ENGINEERING COLLEGE, GHAZIABAD

How to Cite

Use the following formats to cite this article in your research.

APA Style

Srivastava, Riya, Verma, Vidhi, Tiwari, Shivam, Bisariya, Shailendra, & Saxena, Mudit (2024). Design and Implementation of a low power high speed full adder cell for low power applications. International Journal of Advance Research and Innovative Ideas In Education, 10(3), 4584-4589.

MLA Style

Srivastava, Riya, et al. "Design and Implementation of a low power high speed full adder cell for low power applications." International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 3, 2024, pp. 4584-4589.

IEEE Style

Riya Srivastava, Vidhi Verma, Shivam Tiwari, Shailendra Bisariya, and Mudit Saxena, "Design and Implementation of a low power high speed full adder cell for low power applications," International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 3, pp. 4584-4589, 2024.

Vancouver Style

Srivastava Riya, Verma Vidhi, Tiwari Shivam, Bisariya Shailendra, Saxena Mudit. Design and Implementation of a low power high speed full adder cell for low power applications. International Journal of Advance Research and Innovative Ideas In Education. 2024;10(3):4584-4589.

Harvard Style

Srivastava, Riya, Verma, Vidhi, Tiwari, Shivam, Bisariya, Shailendra, & Saxena, Mudit (2024) 'Design and Implementation of a low power high speed full adder cell for low power applications', International Journal of Advance Research and Innovative Ideas In Education, 10(3), pp. 4584-4589.

Chicago Style

Srivastava, Riya, et al. "Design and Implementation of a low power high speed full adder cell for low power applications." International Journal of Advance Research and Innovative Ideas In Education 10, no. 3 (2024): 4584-4589.

Turabian Style

Srivastava, Riya, et al. "Design and Implementation of a low power high speed full adder cell for low power applications." International Journal of Advance Research and Innovative Ideas In Education 10, no. 3 (2024): 4584-4589.