Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm

May 2024
Vol-10, Issue-3
Paper ID: 24035
ISSN: 2395-4396
Downloads: 0

Abstract & Details

Research Area
Electronics and Communication Engineering
Keywords
Sense amplifier flip flop (SAFF) Flip Flop (ff) power consumption speed.
Abstract
A sense amplifier based flip-flop has a low power consumption and high speed. It has a new sense amplifier stage and a new one-ended latch stage. It significantly reduces the power consumption and delays. The proposed SAFF has low voltage operation thanks to MTCMOS optimization. Compared to MSFF, SAFF has lower delay and lower power consumption. Our SAFF is designed for low voltages. We adopt MTCMOS optimization techniques. MTCMOS enables efficient power management by powering down inactive circuits or adjusting voltage levels according to the desired performance. The design is based on 45nm technology and is implemented in cadence virtuoso.

Author Information

# Name Institute / Affiliation
1 Adarsh Bhardwaj ABES Engineering College
2 Amar Jyothi ABES Engineering College
3 Ankit Kumar Bharti ABES Engineering College
4 Amit Pal ABES Engineering College
5 Shailendra Bisariya ABES Engineering College

How to Cite

Use the following formats to cite this article in your research.

APA Style
Bhardwaj, Adarsh, Jyothi, Amar, Bharti, Ankit Kumar, Pal, Amit, & Bisariya, Shailendra (2024). Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm. International Journal of Advance Research and Innovative Ideas In Education, 10(3), 2604-2610.
MLA Style
Bhardwaj, Adarsh, et al. "Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm." International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 3, 2024, pp. 2604-2610.
IEEE Style
Adarsh Bhardwaj, Amar Jyothi, Ankit Kumar Bharti, Amit Pal, and Shailendra Bisariya, "Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm," International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 3, pp. 2604-2610, 2024.
Vancouver Style
Bhardwaj Adarsh, Jyothi Amar, Bharti Ankit Kumar, Pal Amit, Bisariya Shailendra. Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm. International Journal of Advance Research and Innovative Ideas In Education. 2024;10(3):2604-2610.
Harvard Style
Bhardwaj, Adarsh, Jyothi, Amar, Bharti, Ankit Kumar, Pal, Amit, & Bisariya, Shailendra (2024) 'Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm', International Journal of Advance Research and Innovative Ideas In Education, 10(3), pp. 2604-2610.
Chicago Style
Bhardwaj, Adarsh, et al. "Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm." International Journal of Advance Research and Innovative Ideas In Education 10, no. 3 (2024): 2604-2610.
Turabian Style
Bhardwaj, Adarsh, et al. "Advanced Low-Power High-Speed SAFF Implementation with MTCMOS in 45nm." International Journal of Advance Research and Innovative Ideas In Education 10, no. 3 (2024): 2604-2610.

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