An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications

E. Rama Krishna Reddy; R. Tarun; Ch. Ashok Kumar; M. Venkata Rao

An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications

April 2024

Vol-10, Issue-2

Paper ID: 23284

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronics and Communication Engineering

Keywords

4-bit array multiplier adiabatic logic low-power VLSI Near Threshold Region NTAL approach TSMC 65 nm CMOS technology mixer circuit signal and image processing energy efficiency Tanner EDA Spectre simulator and power dissipation optimization

Abstract

This research presents an innovative technique to designing a 4-bit array multiplier for mixer circuit applications in signal and image processing, based on an efficient low-power VLSI methodology. The suggested architecture uses adiabatic approaches in the Near Threshold Region to optimize the trade-off between propagation delay and power dissipation. Multipliers are essential components in many digital electronics contexts, resulting in the birth of many multiplier types customized to certain applications. This technology significantly reduces dynamic and static power dissipation as compared to traditional CMOS technologies. Near Threshold Adiabatic Logic (NTAL) is implemented using a single time-varying power source, which simplifies clock tree management and increases energy efficiency. The suggested design is simulated on the TSMC 65 nm technology node using the Tanner EDA tool and the Spectre simulator, guaranteeing that the optimized outcome is verified. Compared to typical CMOS approaches, while maintaining similar design parameters, there is a significant improvement in power dissipation of roughly 66.6%, 14.4%, and 64.6% for variable frequency, supply voltage, and load capacitance, respectively. Notably, with frequency variation, the load capacitance is held constant at Cload = 10 pF and VDD (max) = 1.2 V; with supply voltage variation, the load capacitance remains constant at Cload = 10 pF and frequency at F = 4 GHz; and with load capacitance variation, the frequency is maintained at F = 4 GHz and the supply voltage at VDD (max) = 1.2 V.

License

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Author Information

#	Name	Institute / Affiliation
1	E. Rama Krishna Reddy	Usha Rama College of Engineering and Technology
2	R. Tarun	Usha Rama College of Engineering and Technology
3	Ch. Ashok Kumar	Usha Rama College of Engineering and Technology
4	M. Venkata Rao	Usha Rama College of Engineering and Technology

How to Cite

Use the following formats to cite this article in your research.

APA Style

Reddy, E. Rama Krishna, Tarun, R., Kumar, Ch. Ashok, & Rao, M. Venkata (2024). An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications. International Journal of Advance Research and Innovative Ideas In Education, 10(2), 3711-3724.

MLA Style

Reddy, E. Rama Krishna, et al. "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications." International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 2, 2024, pp. 3711-3724.

IEEE Style

E. Rama Krishna Reddy, R. Tarun, Ch. Ashok Kumar, and M. Venkata Rao, "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications," International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 2, pp. 3711-3724, 2024.

Vancouver Style

Reddy E. Rama Krishna, Tarun R., Kumar Ch. Ashok, Rao M. Venkata. An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications. International Journal of Advance Research and Innovative Ideas In Education. 2024;10(2):3711-3724.

Harvard Style

Reddy, E. Rama Krishna, Tarun, R., Kumar, Ch. Ashok, & Rao, M. Venkata (2024) 'An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications', International Journal of Advance Research and Innovative Ideas In Education, 10(2), pp. 3711-3724.

Chicago Style

Reddy, E. Rama Krishna, et al. "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications." International Journal of Advance Research and Innovative Ideas In Education 10, no. 2 (2024): 3711-3724.

Turabian Style

Reddy, E. Rama Krishna, et al. "An Efficient Adiabatic 4-Bit Array Multiplier for Low Power Applications." International Journal of Advance Research and Innovative Ideas In Education 10, no. 2 (2024): 3711-3724.