DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES

KALAVA YASWANTH REDDY; JORGIE LEELA MANOHAR; PADAMATI SIDDHARDHA; NELAVALLI RAKESH CHOWDARY

DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES

March 2024

Vol-10, Issue-2

Paper ID: 22849

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

ELECTRONICS AND COMMUNICATION ENGINEERING

Keywords

Reversible logic gate Power dissipation Time delay.

Abstract

In this paper a 4x4 bit reversible multiplier circuit is proposed and designed. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts. Firstly, the Full Adder is Designed using Toffoli gates and then the certain number of Toffoli gates and the designed Full Adders are instantiated to design the reversible multiplier. Xilinx VIVADO simulations are carried out using parameters with a power supply voltage of 5V. The simulation results also confirm that proposed designs give better performance than conventional standard based design. It is also better than the existing counterparts in term of number of gates. Thus, this paper provides the comparison of two multipliers according to their number of gates required and number of constant inputs. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication.

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Author Information

#	Name	Institute / Affiliation
1	KALAVA YASWANTH REDDY	VASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY
2	JORGIE LEELA MANOHAR	VASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY
3	PADAMATI SIDDHARDHA	VASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY
4	NELAVALLI RAKESH CHOWDARY	VASIREDDY VENKATADRI INSTITUTE OF TECHNOLOGY

How to Cite

Use the following formats to cite this article in your research.

APA Style

REDDY, KALAVA YASWANTH, MANOHAR, JORGIE LEELA, SIDDHARDHA, PADAMATI, & CHOWDARY, NELAVALLI RAKESH (2024). DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES. International Journal of Advance Research and Innovative Ideas In Education, 10(2), 924-931.

MLA Style

REDDY, KALAVA YASWANTH, et al. "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES." International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 2, 2024, pp. 924-931.

IEEE Style

KALAVA YASWANTH REDDY, JORGIE LEELA MANOHAR, PADAMATI SIDDHARDHA, and NELAVALLI RAKESH CHOWDARY, "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES," International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 2, pp. 924-931, 2024.

Vancouver Style

REDDY KALAVA YASWANTH, MANOHAR JORGIE LEELA, SIDDHARDHA PADAMATI, CHOWDARY NELAVALLI RAKESH. DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES. International Journal of Advance Research and Innovative Ideas In Education. 2024;10(2):924-931.

Harvard Style

REDDY, KALAVA YASWANTH, MANOHAR, JORGIE LEELA, SIDDHARDHA, PADAMATI, & CHOWDARY, NELAVALLI RAKESH (2024) 'DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES', International Journal of Advance Research and Innovative Ideas In Education, 10(2), pp. 924-931.

Chicago Style

REDDY, KALAVA YASWANTH, et al. "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES." International Journal of Advance Research and Innovative Ideas In Education 10, no. 2 (2024): 924-931.

Turabian Style

REDDY, KALAVA YASWANTH, et al. "DEVELOPING A LOW POWER MULTIPLIER UTILIZING REVERSIBLE LOGIC GATES." International Journal of Advance Research and Innovative Ideas In Education 10, no. 2 (2024): 924-931.