DESIGN OF SINGLE CYCLE RISC-V PROCESSOR

March 2024
Vol-10, Issue-2
Paper ID: 22774
ISSN: 2395-4396
Downloads: 0

Abstract & Details

Research Area
VLSI design
Keywords
RISC-V (Reduced instruction set computer 5th generation) Single cycle processor Instruction Set Architecture (ISA) Data path control unit
Abstract
In the early the computer was stack architecture, later replaced by RISC architecture. The RISC-V Processor features a streamlined set of instructions, a consistent instruction length, an increased number of general-purpose registers, a load-store architecture, and simplified addressing modes. These characteristics contribute to faster execution of individual instructions, leading to improved overall performance and a simplified design. The choice of a RISC is easily understood. The processor is designed for targeting low-cost embedded devices. A Single-Cycle RISC-V Processor is a simplified, yet highly efficient microprocessor architecture that executes instructions in a single clock cycle. This design philosophy emphasizes minimalism, reduced complexity, and enhanced pipelining, which leads to faster execution times and a streamlined hardware structure. By implementing a RISC-V architecture, the processor benefits from an open standard, making it ideal for customization, expansion, and adaptation to various computing applications. The design of a Single-Cycle RISC-V Processor represents a significant leap in microprocessor architecture. Its minimalist design, open-source RISC-V instruction set, and single-cycle execution offer efficiency, scalability, and adaptability, making it an ideal choice for modern computing systems.

Author Information

# Name Institute / Affiliation
1 Talluri Priya Vasireddy Venkatadri Institute of Technology
2 Paruchuri Ushasri Vasireddy Venkatadri Institute of Technology
3 Vetagiri Bhuvana Jyothirmai Vasireddy Venkatadri Institute of Technology

How to Cite

Use the following formats to cite this article in your research.

APA Style
Priya, Talluri, Ushasri, Paruchuri, & Jyothirmai, Vetagiri Bhuvana (2024). DESIGN OF SINGLE CYCLE RISC-V PROCESSOR. International Journal of Advance Research and Innovative Ideas In Education, 10(2), 527-533.
MLA Style
Priya, Talluri, et al. "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR." International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 2, 2024, pp. 527-533.
IEEE Style
Talluri Priya, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai, "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR," International Journal of Advance Research and Innovative Ideas In Education, vol. 10, no. 2, pp. 527-533, 2024.
Vancouver Style
Priya Talluri, Ushasri Paruchuri, Jyothirmai Vetagiri Bhuvana. DESIGN OF SINGLE CYCLE RISC-V PROCESSOR. International Journal of Advance Research and Innovative Ideas In Education. 2024;10(2):527-533.
Harvard Style
Priya, Talluri, Ushasri, Paruchuri, & Jyothirmai, Vetagiri Bhuvana (2024) 'DESIGN OF SINGLE CYCLE RISC-V PROCESSOR', International Journal of Advance Research and Innovative Ideas In Education, 10(2), pp. 527-533.
Chicago Style
Priya, Talluri, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR." International Journal of Advance Research and Innovative Ideas In Education 10, no. 2 (2024): 527-533.
Turabian Style
Priya, Talluri, Paruchuri Ushasri, and Vetagiri Bhuvana Jyothirmai. "DESIGN OF SINGLE CYCLE RISC-V PROCESSOR." International Journal of Advance Research and Innovative Ideas In Education 10, no. 2 (2024): 527-533.

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