Analysis and Design 10 bit of Current – Steering  Digital to Analog Converter in CMOS  Technology

Pooja J.Dani; Mr.Yash Sharma

Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology

May 2016

Vol-2, Issue-3

Paper ID: 2172

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Very large scale integration

Keywords

Binary Weighted Thermometer Segmented Digital to Analog Conversion Glitch

Abstract

The pressure to reduce cost in mass market communication devices such as cable modems and digital set-top boxes has created a need for embedded high-speed high-resolution digital-to-Analog converters (DACs). This thesis discusses the different architectures of current- steering digital-to-Analog converter (CS-DAC). Reasons of selecting binary-weighted architecture are low complexity, small area and less power consumption in comparison of other architectures. 14-bit CS-DAC is implemented and performance parameters are checked.

License

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

Author Information

#	Name	Institute / Affiliation
1	Pooja J.Dani	Sal Institute Technology and Engineering Reasearch
2	Mr.Yash Sharma	Sal Institute Technology and Engineering Reasearch

How to Cite

Use the following formats to cite this article in your research.

APA Style

J.Dani, Pooja & Sharma, Mr.Yash (2016). Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology. International Journal of Advance Research and Innovative Ideas In Education, 2(3), 385-394.

MLA Style

J.Dani, Pooja, and Mr.Yash Sharma. "Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology." International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, 2016, pp. 385-394.

IEEE Style

Pooja J.Dani and Mr.Yash Sharma, "Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology," International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, pp. 385-394, 2016.

Vancouver Style

J.Dani Pooja, Sharma Mr.Yash. Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology. International Journal of Advance Research and Innovative Ideas In Education. 2016;2(3):385-394.

Harvard Style

J.Dani, Pooja & Sharma, Mr.Yash (2016) 'Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology', International Journal of Advance Research and Innovative Ideas In Education, 2(3), pp. 385-394.

Chicago Style

J.Dani, Pooja and Mr.Yash Sharma. "Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 385-394.

Turabian Style

J.Dani, Pooja and Mr.Yash Sharma. "Analysis and Design 10 bit of Current – Steering Digital to Analog Converter in CMOS Technology." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 385-394.