Performance Analysis of different MUX for FPGA

Prof. S. M.Turkane; N.V.Ambedkar; S.V.Kaname; T.V.Kharde

Performance Analysis of different MUX for FPGA

April 2016

Vol-2, Issue-3

Paper ID: 2070

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

Electronics and Telecommunication

Keywords

CMOS LUT 2:1Multiplexer 4:1Multiplexer 8:1 Multiplexer.

Abstract

A Field-Programmable Gate Array is an FPD featuring a general structure that permits very high logic capacity. FPGAs offer higher ratio of flip-flops to logic resources than do CPLDs. The main problem is power dissipation than speed and area. In this paper, the primary and important issue within the low power MOSFET circuit is power dissipation. The methods we use for reducing power and energy dissipation in conventional CMOS circuit comprise reducing the power supply voltages and the nodes, capacitances or switch activities with efficient charge recovery logic. This paper also determine with multiplexer to improve the ability and design a 2:1, 4:1 and 8:1 multiplexer with CMOS transistor. All the results of this paper are simulated on SYMICA tool realized in 22nm and 32nm technology.

License

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Author Information

#	Name	Institute / Affiliation
1	Prof. S. M.Turkane	PREC Loni,
2	N.V.Ambedkar	PREC Loni,
3	S.V.Kaname	PREC Loni,
4	T.V.Kharde	PREC Loni,

How to Cite

Use the following formats to cite this article in your research.

APA Style

M.Turkane, Prof. S., N.V.Ambedkar, S.V.Kaname, & T.V.Kharde (2016). Performance Analysis of different MUX for FPGA. International Journal of Advance Research and Innovative Ideas In Education, 2(3), 87-93.

MLA Style

M.Turkane, Prof. S., et al. "Performance Analysis of different MUX for FPGA." International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, 2016, pp. 87-93.

IEEE Style

Prof. S. M.Turkane, N.V.Ambedkar, S.V.Kaname, and T.V.Kharde, "Performance Analysis of different MUX for FPGA," International Journal of Advance Research and Innovative Ideas In Education, vol. 2, no. 3, pp. 87-93, 2016.

Vancouver Style

M.Turkane Prof. S., N.V.Ambedkar, S.V.Kaname, T.V.Kharde. Performance Analysis of different MUX for FPGA. International Journal of Advance Research and Innovative Ideas In Education. 2016;2(3):87-93.

Harvard Style

M.Turkane, Prof. S., N.V.Ambedkar, S.V.Kaname, & T.V.Kharde (2016) 'Performance Analysis of different MUX for FPGA', International Journal of Advance Research and Innovative Ideas In Education, 2(3), pp. 87-93.

Chicago Style

M.Turkane, Prof. S., et al. "Performance Analysis of different MUX for FPGA." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 87-93.

Turabian Style

M.Turkane, Prof. S., et al. "Performance Analysis of different MUX for FPGA." International Journal of Advance Research and Innovative Ideas In Education 2, no. 3 (2016): 87-93.