Design of 6T SRAM with 8T Self-gating Ternary CAM cell using XOR logic

Electronics & Telecommunication Engineering

To reduce the power consumption of the TCAM cell when we search the data. Most memory devices store and retrieve data by addressing specific memory location. As a result this path often becomes the limiting factor for the systems that rely on fast memory access. In this paper to design six transistors based SRAM design with eight transistors of two side self gating TCAM and to design four transistors using transmission gate logic function of XOR based TCAM. This design is to increase the matched line search process and to reduce the overall dynamic power consumption level of TCAM array design. Our proposed work is to design CMOS based RAM and Ternary CAM memory architecture. This design is used to find matched line data effectively and to reduce the leakage power level for match line searching process. To design transmission gate logic for matched line searching process. This process is to apply the TCAM cell architecture and to reduce the dynamic power consumption. Our work is to analysis the data store and search, data matching operation and to maintain the input voltage level then to optimize the Vdd to ground power leakage level. This system is used to identify the input data and search data then to manage the data matching level to improve the matched line data searching process. Proposed system is to consume less power and also reduce the leakage power level and less area consumption. This system is to require less external voltage sources. This system is no need to register element separately.

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