IMPLEMENTATION OF PICORV-32 USING ASIC DESIGN

ELECTRONICS AND COMMUNICATION

The VHDL hardware description language was used to create the core, which allows for the addition of customised, optimised hardware units for particular operation. The consequences on power consumption and area, and processing power are all investigated. RISC-V was created with the purpose of creating a practical ISA that was open-sourced, academically accessible, and royalty-free to use in any hardware or software design. A RISC-V processor core implementation for SoC design is presented. In 0.6m and 0.13m technology, the distinctions between the hypothetical FPGA implementation and the standard cell realisations. The VHDL hardware description language was used to create the core, which allows for the addition of customised, optimised hardware blocks for particular operations. The consequences in terms of area and power are analysed.

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