A novel approach of vedic multiplier using modified CSA with optimized system performance

Electronic and Communication Engineering

Vedic mathematics is a Design of mathematics followed in ancient Indian and it is applied in various trees of mathematical calculations. a novel algorithm is designed on Vedic mathematics using bit reduction technique for binary multiplication. There is a total count of 16 vedic sutras or formulas and 13 sub-sutras to ou source the different mathematical operation. For carrying out the multiplication operation there are two sutras- urdhva tiryakbhyam and nikhilam sutra. In this two, the urdhva tiryakbhyam sutra is discussed in this paper to design a multiplier and compared the area and speed with array multiplier. Vedic multiplier is structured using modified square-root carry select adder (MSQRT-CSA). They considered the bring out with numerous adders like CSA, Carry look-ahead adder (CLA), Square root CSA (SQRT-CSA). Collated with other methods, multiplier is faster in MSQRT-CSA. Vedic multiplier is proposed and contrasted with array multiplier in Complex number multiplication is used. The remainder is derived from this sutra by lowering the remainder bit size to N-2 bit. At this moment, the no.of bits of the remainder is statically maintained as N-2 bits. The phase of the proposed algorithm is enhanced with equipoising the power and area. Even though there is a deviation in lower order bits, this method shows maximum difference in higher bit lengths.

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