FPGA based CRC using LUT

Electronics and Communication Engineering

Error detection is an inevitable stage in data transmission. The current scenario in networking environment is high speed data transmission. It is necessary to increase speed of CRC generation to synchronize with the challenging speed of transmitting data. The main objective of this paper is to design a CRC-256 code generator for large input data blocks to increase the effectiveness of CRC codes in error detection. FPGA implementation of CRC code generator could be done in two versions. The first version of the generator designed using linear feedback shift registers is studied. Identifying the serial architecture, a recursive formula the parallel design was derived. As the second version, an accelerated CRC-256 generator designed using an acceleration technique for CRC generation. The implementation of both the CRC-256 generators was carried out in Verilog hardware description language. Simulation and functional verification Xilinx Design Suite 14.2 and Vivado is utilised. A look table-based generator is designed to compare efficiency.

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