A Study of Use of QCA Technology for Nano Circuit Libraries

ELECTRONICS & COMMUNICATION ENGINEERING

The proposed research work uses the QCA technology to design digital circuits in an optimized manner at the nano level. Initially, the conventional structures such as 2’s complement adder and subtract or, Baugh-Wooley multiplier is presented to exploit the advantages of QCA. Afterwards, various existing XOR gate structures are analyzed. It is identified that there is a possibility to optimize the XOR gate layout. So, an enhanced XOR gate layout structure is presented in a single layer. The XOR gate structure is more significant in many applications such as a Half Adder, Full Adder, Equality Byte Comparator, Parity generator and checker, etc.,. All these applications are implemented by enhanced XOR gate layout structure. The proposed structures are implemented without using crossovers, which reduces the number of cells required and performs the functionality in a cost efficient manner with higher speed. Over the latest twenty years, contemporary Complementary Metal Oxide Semiconductor (CMOS) circuits overpowered the Integrated Circuit (IC) innovation in a quick way. The XOR entryway structure is huger in various applications, for instance, a Half Adder, Full Adder. All of these applications is realized by improved XOR gate design structure. The proposed structures are realized without using mixtures, which reduces the amount of cells required and plays out the handiness in a cost beneficial manner with higher speed. A brief timeframe later, unique existing XOR gate structures are analyzed. It is perceived that there is probability to smooth out the XOR entryway design. Thusly, an upgraded XOR gate configuration structure is presented in a lone layer.

This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.