Comparison of Effective area Efficient Architectures for Modified SQRT CSLA

electonics and communication engineering

Carry Select Adder (CSLA) is one of the fastest efficient adders which are used in many data-processing processors to perform fast arithmetic functions. CSLA is called efficient adder because of less delay and reduced size. In this paper 16 bit, 32 bit, 64 bit and 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA The proposed work conveys that it uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. The performance factors of the proposed design are evaluated in terms of delay, area, power and their products by simulation tool and implemented in FPGA kit. The results analysis shows that the proposed modified BEC CSLA structure is better than the regular BEC SQRT CSLA. This paper introduces an unique method that replaces the BEC using common Boolean logic. This paper proposes an efficient method which replaces the BEC using D latch. Experimental results are compared and the result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power..

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