Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique

b.revathi; k swaroop

Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique

July 2020

Vol-6, Issue-4

Paper ID: 12421

ISSN: 2395-4396

Downloads: 0

Abstract & Details

Research Area

electonics and communication engineering

Keywords

full adder

Abstract

With the advancements in the technology and increase in the usage of laptops, cellular phones, ipads, Internet of Things (IoT) devices, and other portable communication systems, there are many applications requiring high speed, small area, and low power consumption. So there is a need of circuits with low energy consumption for the design of system components and application specific processors. The aim of this work is to design 1-bit full adder circuit using full-swing GDI to reduce power consumption, in addition to achieve full-swing output. This paper presents a design which provides full swing output for logic 1 and logic 0 for 1-bit full adder cell and reduces power consumption. In this design full adder consists of two XOR gate cells and one cell of 2x1 multiplexer (MUX). The performance of the proposed design compared with the different logic style for full adders.

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Author Information

#	Name	Institute / Affiliation
1	b.revathi	gandhiji institute of science and technology
2	k swaroop	gandhiji institute of science and technology

How to Cite

Use the following formats to cite this article in your research.

APA Style

b.revathi & swaroop, k (2020). Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique. International Journal of Advance Research and Innovative Ideas In Education, 6(4), 1044-1052.

MLA Style

b.revathi, and k swaroop. "Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique." International Journal of Advance Research and Innovative Ideas In Education, vol. 6, no. 4, 2020, pp. 1044-1052.

IEEE Style

b.revathi and k swaroop, "Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique," International Journal of Advance Research and Innovative Ideas In Education, vol. 6, no. 4, pp. 1044-1052, 2020.

Vancouver Style

b.revathi, swaroop k. Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique. International Journal of Advance Research and Innovative Ideas In Education. 2020;6(4):1044-1052.

Harvard Style

b.revathi & swaroop, k (2020) 'Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique', International Journal of Advance Research and Innovative Ideas In Education, 6(4), pp. 1044-1052.

Chicago Style

b.revathi and k swaroop. "Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique." International Journal of Advance Research and Innovative Ideas In Education 6, no. 4 (2020): 1044-1052.

Turabian Style

b.revathi and k swaroop. "Design and Analysis of Low Power High Speed Full Adder Cell using Modified GDI Technique." International Journal of Advance Research and Innovative Ideas In Education 6, no. 4 (2020): 1044-1052.