OPTIMIZED DESIGN OF AM OPERATOR USING MODIFIED KOGGESTONE ADDER

ELECTRONICS AND COMMUNICATION

Multipliers are the inevitable component in most of the Digital Signal Processing applications. Multipliers with High speed and low area are of substantial importance from the view point of research. To obtain high speed, the multiplier utilizing modified koggestone adders are implemented in this work. The design and implementation of Add-Multiply (AM) unit constituting modified koggestone block improves the overall performance of the multiplier. The conventional AM unit using Modified Booth (MB) multiplier make use of CSA and CLA adders which limits its performance due to delay involved and hardware complexity. Fast adder introduced in the design speeds up the entire process of multiplication. It further reduces the area occupancy and considerable power improvements are achieved. The speed of conventional multiplier design can be enhanced by employing modified koggestone adder in the AM design and it attempts to reduce the delay of conventional design using CSA and CLA adder trees. Therefore an area effective and speed optimized AM unit is proposed in order to overcome the drawbacks of conventional design. The analysis of both existing and proposed techniques are clearly shown. AM units are simulated using Xilinx ISE 14.7 for performance analysis

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