IMPLEMENTATION OF USB 3.0 WITH LOW POWER 8B/10B ENCODER/DECODER

electonics and communication engineering

The design and the implementation of 8x10 encoder and 10x8 decoder by using 3 bit down ripple counter Has been proposed in this paper .In a ripple counter , a flip-flop output transition serves as source for triggering other flipflops .The clock skew problem can be reduced by using this ripple counter technique. By reducing clocks skew we can reduce the power consumption of hardware. So ripple counter technique has been used in this paper for the purpose of reducing the power consumption of the encoder and decoder circuits .The RTL schematic of 8x10encoder with ripple counter is shown in fig 9 and the fig 10 shows the RTL schematic 10x8 decoder with ripple counter .The clock power of an encoder circuit is reduced by11.11% at a frequency of 20mhz and the chip power of an encoder is reduced by 2.70% both the clock power and on chip power of decoder circuit are reduced 8.33% and 0% respectively at same frequency .The clock power and on the chip power of decoder is reduced to 10.17%and 22.15%at a frequency range of 200 MHz .Similarly the clock power and on chip power of a decoder are reduced to 7.44% and 4.33% at the same frequency. By using verilog HDL designing of 3 circuits i.e..... 8x10 encoder 10x8 decoder and 3 bit down ripple counter are done and the same are simulated in model sim 10.3. Xilinx ISE suit 13.4 has been used for the purpose of RTL, technology schematics and power report of the implemented circuit. By using FPGA of kintex 7 family the verification of encoder and decoder with ripple counter has been done

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