FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE
Abstract & Details
Research Area
Elevtronics Engineering, Electronics and communication Engineering, VLSI
Keywords
Fault tolerant system
fifth modular redundancy
time redundancy
TMR
Reliability system
Embedded systems.
Abstract
This article validates the reduction in hardware utilization to establish a reliable system at the cost of time. Redundancy is a technique to improve reliability and availability of a system. Triple modular redundancy uses three functionally equivalent units to provide a redundant backup and it has a majority voter circuit which produces a single output. An alternative way to have a fault less system and the idea of boosting the dependency of a system is fault tolerant system. The most fundamental method used for the fault tolerant system is triple modular redundancy in which the majority voter circuit obtains fault free response. Traditionally, for building a fifth modular redundant system, five different modules are required which increases the hardware substantially. Hence, to reduce the hardware, we have established a fifth modular redundant system using a combination of triple modular redundancy and time redundancy. In this study, we have used 2bit multiplier using different modular redundancy modules to verify our purpose.
License
This work is licensed under a Creative
Commons
Attribution-ShareAlike 4.0 International License.
Author Information
| # | Name | Institute / Affiliation |
|---|---|---|
| 1 | Yamini Agrawal | Shri Ramdeobaba College of Engineering and Management, Nagpur |
| 2 | Shavi Goel | Shri Ramdeobaba College of Engineering and Management, Nagpur |
| 3 | Priyanka Das | Shri Ramdeobaba College of Engineering and Management, Nagpur |
| 4 | Prof. Prasheel Thakre | Shri Ramdeobaba College of Engineering and Management, Nagpur |
How to Cite
Use the following formats to cite this article in your research.
APA Style
Agrawal, Yamini, Goel, Shavi, Das, Priyanka, & Thakre, Prof. Prasheel (2019). FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE. International Journal of Advance Research and Innovative Ideas In Education, 5(2), 2728-2738.
MLA Style
Agrawal, Yamini, et al. "FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE." International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, 2019, pp. 2728-2738.
IEEE Style
Yamini Agrawal, Shavi Goel, Priyanka Das, and Prof. Prasheel Thakre, "FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE," International Journal of Advance Research and Innovative Ideas In Education, vol. 5, no. 2, pp. 2728-2738, 2019.
Vancouver Style
Agrawal Yamini, Goel Shavi, Das Priyanka, Thakre Prof. Prasheel. FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE. International Journal of Advance Research and Innovative Ideas In Education. 2019;5(2):2728-2738.
Harvard Style
Agrawal, Yamini, Goel, Shavi, Das, Priyanka, & Thakre, Prof. Prasheel (2019) 'FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE', International Journal of Advance Research and Innovative Ideas In Education, 5(2), pp. 2728-2738.
Chicago Style
Agrawal, Yamini, et al. "FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 2728-2738.
Turabian Style
Agrawal, Yamini, et al. "FPGA BASED RELIABILITY SYSTEM USING MODULAR REDUNDANCY TECHNIQUE." International Journal of Advance Research and Innovative Ideas In Education 5, no. 2 (2019): 2728-2738.
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